1. Field of the Invention
The present invention relates to a semiconductor neural network, and more particularly, it relates to structure for improving integration density of a semiconductor neural network.
2. Description of the Background Art
In recent years, various electronic circuits have been modeled on human nerve cells (neurons). One of such neuron models is called a Hopfield model. This Hopfield model is now briefly described.
FIG. 1 schematically shows the structure of a unit which is modeled on a neuron. This unit i includes an input part A which receives signals from other units k, j, and the like, a conversion part B which converts the received inputs along a predetermined rule and an output part C which outputs the results of conversion. The input part A has weights (synapses) W showing strengths of connection between the respective units. Thus, a weight Wik is added to a signal Sk from the unit k, which is transmitted to the conversion part B. Each weight W can take a positive value, a negative value or zero. The conversion part B outputs the sum net of the inputs S, to which the weights W are added, through a predetermined function f. An output S.sub.i from the unit i at a time t is provided as follows: ##EQU1## A threshold function shown in FIG. 2A or a sigmoid function shown in FIG. 2B is generally employed a the function f.
The threshold function shown in FIG. 2A is a unit step function which outputs "1" when the sum net(i) of the inputs exceeds a predetermined threshold value .theta., while otherwise outputting "0".
The sigmoid function shown in FIG. 2B is a nonlinear, monotonously increasing function which is expressed as: EQU f=1/[1+exp(-net(i))]
This sigmoid function, which is in a range of zero to 1, approaches "0" as the sum net(i) of the inputs decreases, while approaching "1" as the sum net(i) increases. This sigmoid function outputs "0.5" when the sum net(i) is "0".
A predetermined threshold value .theta. may be added to the aforementioned sigmoid function, thereby to use a function which is expressed as: EQU f=1/[1+exp(-net(i)+.theta.)]
The aforementioned unit is modeled on a vital cell which receives stimuli from other neuron to generate an output or to fire when the sum of the stimuli exceeds a given value. The Hopfield model provides an operating model of a network which is formed by a plurality of such neurons.
When initial states are supplied to respective neuron units in the aforementioned equations (1), the states of the respective neuron units are thereafter entirely determined in principle by simultaneously applying the aforementioned two dynamic equations (1) to all the neuron units and solving the same. If the number of the units increases, however, it is almost impossible to examine and grasp the states of the respective units one by one for programming weight and bias values in order to provide optimum solutions to target problems. Therefore, Hopfield introduces an energy function which is defined as: ##EQU2## as a quantity expressing the property of the overall system (neural network) in place of the states of the respective units. Symbol Ii represents a self-bias value which is specific to a unit i. Hopfield has indicated that, when a weight (synapse load) Wij is symmetrical as Wij=Wji, each unit changes its state to regularly minimize the aforementioned energy function to the local minimum, and proposed to apply this model to programming of the weight Wij. The model having the aforementioned energy function is called a Hopfield model. The aforementioned model is generally expressed as follows: ##EQU3## as a discrete time model. Symbol n represents a discrete time. Hopfield himself has indicated that this Hopfield model is realized particularly in high accuracy when the slope of the function f showing input/output characteristics is abrupt (a function approximate to a unit step function with which almost all outputs take values close to "0" or "1").
A neural network is constructed in a VLSI (very large scale integrated circuit) in accordance with the Hopfield model, as disclosed in "Computer", a magazine issued by IEEE (Institute of Electrical and Electronics Engineers), March 1988, pp. 41-49, for example.
FIG. 3 schematically shows overall structure of a conventional neural network integrated circuit. Referring to FIG. 3, the conventional neural network integrated circuit includes a resistive matrix 100 which is formed by an array of resistive coupling elements having prescribed weights and an amplifier 101 which amplifies potentials on data input lines included in the resistive matrix 100 and feeds back the amplified signals to input parts of the resistive coupling elements. The resistive matrix 100 includes data input lines and data output lines which are arrayed orthogonally to the data input lines, as hereinafter described in detail. Interconnection states of the data input lines and the data output lines through the resistive coupling elements are programmable.
A row decoder 102 and a bit decoder 103 are provided in order to program the states of the respective resistive coupling elements included in the resistive matrix 100, i.e., the interconnection states between the data input lines and the data output lines. The row decoder 102 selects a row of the resistive matrix 100, while the bit decoder 103 selects a column thereof.
The circuit further includes an input/output data register 104 which temporarily latches input/output data, a multiplexer 105 which connects the input/output data register 104 to the data input lines or the data output lines included in the resistive matrix 100 in response to a data write/read mode and an interface (I/O) 106 for connecting the input/output data register 104 to the exterior of the circuit, in order to input or output data. This neural network is integrated on a semiconductor chip 200. FIG. 4 illustrates exemplary structure of the resistive matrix 100 shown in FIG. 3.
Referring to FIG. 4, the resistive matrix 100 includes data input lines A1 to A4 and data output lines B1 and B1, B2 and B2, B3 and B3, and B4 and B4. Resistive coupling elements 1 are provided on respective crosspoints of the data input lines A1 to A4 and the data output lines B1 and B1 to B4 and B4. The resistive coupling elements 1 can enter open, excitatory and inhibitory states. The states of the resistive coupling elements 1 can be programmed from the exterior for an applied problem. While those being in the open states are shown with no resistance marks in FIG. 4, the resistive coupling elements 1 are provided in all the crosspoints between the data input lines and the data output lines. The resistive coupling elements 1 transmit potential levels on the corresponding data output lines onto the corresponding data input lines in accordance with the programmed states respectively.
The input lines A1 to A4 are respectively provided with amplifier circuits C1 to C4 which amplify the data on the corresponding data input lines and transmit the same onto the corresponding data output lines. Each of the amplifier circuits C1 to C4 has two inverting amplifiers 2a and 2b, which are connected in series with each other. The inverting amplifier 2a inverts the potential on an input line Ai and transmits the same onto an output line Bi. The inverting amplifier 2b transmits the data on the input line Ai onto an output line Bi.
Each of the coupling elements 1 connects the output of an amplifier Ci to the input of another amplifier Cj. FIG. 5 shows exemplary structure of each coupling element.
Referring to FIG. 5, the resistive coupling element 1 includes resistor elements R+ and R-, switching elements S1, S2, S3 and S4 and random access memory cells 150 and 151. An end of the resistor element R+is connected to a source potential V.sub.DD. An end of the resistor element Ris connected to another source potential V.sub.SS. The switching element S1 is on-off controlled by the output of the inverting amplifier 2b. The switching element S2 is on-off controlled by information stored in the random access memory cell 150. The ON/OFF state of the switching element S3 is set by information stored in the random access memory cell 151. The switching element S4 is on-off controlled by the output of the inverting amplifier 2a.
The storage contents of the random access memory cells 150 and 151 can be programmed from the exterior. Although not clearly shown in FIG. 4, word lines W1 and W2 for row selection and bit lines BL for column selection are arranged for respective ones of the random access memory cells 150 and 151, for selection by the row decoder 102 and the bit decoder 103 shown in FIG. 3. Thus, such word lines WL and bit lines BL are arrayed in parallel with the data input lines Ai and data output lines Bi in the resistive matrix 100, respectively.
In the structure shown in FIG. 5, the output of the amplifier circuit Ci directly supplies no current to the corresponding input line. Thus, output load capacitance of the amplifier Ci is reduced. The resistor elements R+ and R- are current limit resistors. The coupling element 1 can enter one of three states in accordance with program states of the random access memory cells 150 and 151. The three states include an excitatory connection state in which the switching element S2 is in an ON state (active state), an inhibitory connection state in which the switching element S3 is in an active state (ON state) and an open connection state in which both of the switching elements S2 and S3 are in inactive states (OFF states). When potential levels of the output lines Bi and of the amplifier circuit C match with the programmed connection state of a given resistive coupling element 1, a current flows to the corresponding input line Ai from either the source potential V.sub.DD or the other source potential (ground potential V.sub.SS. When the resistive coupling element 1 is programmed in the open connection state, no current is transmitted to the input line Ai regardless of the output state of the amplifier circuit Ci.
When the aforementioned circuit model is associated with a neuron model, the amplifier circuit Ci corresponds to a neuron body (conversion part B in FIG. 1). The interconnections A1 to A4, B1 to B4 and B1 to B4 correspond to the data input and output line structure parts (dendrites and axons) shown in FIG. 1. The resistive coupling elements 1 correspond to the synapse load parts provided between the neurons for adding weights. The operation is now briefly described.
The model shown in FIG. 4 is often called a connectionist model. In this model, each neuron unit (amplifier circuit Ci) merels thresholds an input signal, i.e., outputs a signal which is responsive to the value of the input signal with respect to a predetermined threshold value. Each resistive coupling element 1 connects the output of a given amplifier circuit Ci to the inputs of other amplifier circuits Cj. Thus, the state of each amplifier circuit Ci is determined by the states of all the remaining amplifier circuits Cj. When a given amplifier circuit Ci detects the current of a corresponding input line Ai (i=1 to 4), the output of the amplifier circuit Ci is provided as follows: ##EQU4## where Vin(i) and Vout(i) represent input and output voltages of the amplifier circuit Ci which is connected to the data input line Ai, Ii represents a current flowing in one resistive coupling element 1 and Wij represents conductance of the resistive coupling element connecting the amplifier circuit Ci, which is connected to the data input line Ai, with the amplifier circuit Cj, which is connected to the data input line Aj. The output voltage Vout(i) of each amplifier circuit Ci is provided by the transfer characteristic of the amplifier circuit Ci itself. The voltage of the input line Ai of a given amplifier circuit Ci is provided by the sum of currents flowing into the input line Ai. This voltage is adjusted to a value where the total current is zero. That is, the total energy of this electronic network is minimized at this time. The output of the amplifier Ci at that time supplies the output data.
Each amplifier circuit Ci is formed by a CMOS inverter, for example, the input impedance of which is high and has the aforementioned nonlinear, monotonously increasing threshold function. In this case, the following relation holds from the aforementioned condition that the total current is zero: ##EQU5## where symbol Iij represents a current flowing in the resistor of the resistive coupling element which is controlled by the output of the amplifier circuit Ci connected to the input line Ai. Symbol .DELTA. Vij represents potential difference across the resistive coupling element, which potential difference is provided as follows: ##EQU6## Symbol Rij represents resistance of the resistive coupling element, which resistance is provided as R+ or R-. Thus, the voltage Vin(i) is the total sum of all outputs of the amplifier circuits which are connected to the data input lines Ai.
The above is analog calculation, which is performed within the resistive matrix 100 in a parallel manner. However, both the input and output data are digital data. Actual arithmetic operation is now briefly described with reference to FIG. 4.
The neural network is initialized when input data are supplied onto the respective input lines Al to A4 through the register 10, so that the input lines Al to A4 are charged at values corresponding to the input data.
Output potentials of the amplifier circuits C1 to C4 are first changed in response to the charging potentials supplied to the input lines Al to A4. Such potential changes on the data output lines are fed back to the data input lines Al to A4 through corresponding resistive coupling elements. The potential levels fed back to the respective data input lines Al to A4 are determined by program states of the respective resistive coupling elements 1. When a given resistive coupling element 1 is programmed in excitatory connection, a current flows from the source potential V.sub.DD to an input line Ai. When the resistive coupling element 1 is programmed in an inhibitory connection state, on the other hand, a current flows into the data input line Ai from the ground line V.sub.SS. Such operations progress in a parallel manner except for resistive coupling elements which are in open connection states so that currents flowing into a given data input line Ai are added up in an analog manner thereby to change the potential at the data input line Ai. When such potential change of the data input line Ai exceeds the threshold voltage of a corresponding amplifier circuit Ci (inverting amplifiers 2a and 2b), the output potential of this amplifier circuit Ci is changed. Such a state is repeated and the outputs of the amplifier circuits Ci are so changed as to satisfy the aforementioned condition that the total current is zero. The state of the network is finally stabilized to satisfy the aforementioned equation (2) for the stabilized state.
After the state of the neural network is stabilized, the output voltages of the respective amplifier circuits Ci are stored in a register (register 10 or a separately provided output register; register 104 in FIG. 3) and thereafter read out. A decision of the stabilized state of the neural network is set by a predetermined time after data input, or made by directly comparing register values stored in the output register with each other wherein, a decision is made that the neural network is stabilized when difference between the compared output data reaches a prescribed value, to obtain the output data.
As described above, data minimizing the energy of the neural network are outputted as the output data. The resistive matrix 100 stores certain patterns or certain data in accordance with the program states of the resistive coupling elements 1. The neural network, which can decide match/mismatch of the stored patterns or data and input data, also functions as an associative memory or a pattern discriminator.
Structure known as a single-layer perceptron circuit is obtained by removing feedback paths from the data output lines Bi and Bi to the data input lines Aj from the resistive matrix 100 shown in FIG. 4. This perceptron circuit, which develops various algorithms, can be multi-layered to construct a flexible system.
In the aforementioned conventional neural network, the connection strengths of the coupling elements are programmed by writing data in the random access memory cells provided in the coupling elements. In order to write the data in the respective random access memory cells, there are required row and column selecting lines (word lines and bit lines) for selecting the memory cells, signal lines for transmitting control signals for writing the data in the memory cells and the like. Such row and column selecting lines and control signal lines must be provided independently of the data input/output lines of the neural network itself. As understood from FIG. 5, the respective memory cells are coupled with the data input/output lines of the neural network through the switching elements, and not directly coupled with the same. Thus, an area occupied by signal interconnections in the resistive matrix part is increased to significantly obstruct improvement in density of integration of the semiconductor neural network.
It may be considered to multi-layer the row and column selecting lines and the data input/output lines of the neural network, thereby to reduce the interconnection area. In this case, however, the fabrication process is complicated to lead to reduction in fabrication yield.
When the aforementioned random access memory cells are employed, further, a long period of time is required to program the states of the coupling elements since it is impossible to simultaneously write desired data in all memory cells.
On the other hand, a solid state scanning element such as a solid state image pickup element is known as a device for optically reading and processing image information. As shown in FIG. 6A, such a solid state image pickup element is formed by a matrix of photodiodes which serve as light receiving elements and MOS (metal-insulating film-semiconductor) transistors which serve as switching elements for reading signal charges of the photodiodes.
Referring to FIG. 6A, each photodiode is formed by a P-type semiconductor layer 255 which is epitaxially grown on an N-type semiconductor substrate 250 and an N.sup.+ -type semiconductor impurity region 251 which is formed on a prescribed region of the P-type semiconductor layer 255. Each MOS transistor for detecting the signal charge stored in the photodiode is formed by a thin insulating film 254 of SiO.sub.2 or the like formed on the P-type semiconductor layer 255, a gate electrode 253 of polysilicon or the like and an N.sup.+ -type impurity region 252 which is connected to a signal line S. The gate electrode 253 of polysilicon, for example, is connected to a control signal line (vertical scanning line) G. FIG. 6B illustrates a equivalent circuit of the photo detector shown in FIG. 6A.
A photodiode PD is reverse-biased and generates a photoelectric current when it is supplied with light. The generated photoelectric current is transmitted onto a signal line S by bringing a corresponding switching element SW into an ON state.
In such a solid state image pickup element, each photodiode and each MOS transistor form one pixel as shown in FIGS. 6A and 6B, and such pixels are arrayed to form a matrix. The control signal line G, which is also called a vertical scanning line, simultaneously brings vertically arrayed pixels into ON states. The signal line S is provided in correspondence to horizontally arrayed pixels, so that a row of horizontally arrayed pixels are simultaneously selected by the control signal line G and transmitted onto the signal line S are pixel data.
FIG. 7 schematically illustrates the structure of a solid state scanning element having a row of a photodiode array PDA. Referring to FIG. 7, the solid state scanning element includes the photodiode array PDA, which is formed by n photodiodes PDl to PDn. The respective photodiodes PDl to PDn are provided with switching transistors SWl to SWn for transmitting data onto a signal line S. A shift register SR is provided to sequentially bring the switching transistors SWl to SWn into ON states through control signal lines Gl to Gn thereof in response to two-phase, non-overlapping clock signals .phi. and .phi., in order to sequentially read out data from the photodiode array PDA. This shift register SR enters an operating state in response to a starting pulse .phi.s, and sequentially brings signal potentials at the control signal lines G1 to Gn to high levels one by one in response to the clock signals .phi. and .phi.. Thus, the data stored in the photodidoes PDl to PDn included in the photodiode array PDA are sequentially read out on the signal line S.
This solid state scanning element cannot simultaneously read out the signal charges of all the photodiodes although all the photodiodes can simultaneously receive optical pattern information, and hence the data are read out in a serial manner. Thus, the solid state scanning element cannot process information at a high speed.